Potential of Dynamic Binary Parallelization

As core counts continue to grow in modern microarchitectures, automatic parallelization technologies are becoming increasingly important to fill the gap between hardware that has increased parallelism and software that is still designed for sequential execution. In previous research, we have proposed a novel dynamic binary parallelization scheme called T-DBP, which leverages hot traces to provide a large instruction window without introducing spurious control and data dependencies. In this paper, we conduct a limit study to estimate the maximum possible performance of T-DBP on the SPEC CPU2000 benchmark suite. Our results indicate an average speedup of 9.18x and 22.34x over sequential execution for the integer and floating point benchmarks, respectively. We also explain this high speed increase by quantitatively demonstrating that T-DBP uses runtime information to overcome two key handicaps of compile-time parallelization techniques. By artificially emulating the effects of these handicaps in T-DBP, the average speedup shrinks to 4.51x (integer) and 9.36x (floating point), respectively.